P&R Engineer

Job Description

• Perform RTL to GDSII design flow, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, EM/IR;

• Perform Full chip DRC/LVS/ANT/DFM;

• Participate in next generation physical design, methodology and flow development.

Job requirements

• Bachelor degree or Master degree in Microelectronics;

• Be familiar with RTL to GDSII design flow;

• Be familiar with EDA tool;

• Successful track records of taping out complex, 65/40/28 nm SOC chips;

• Be familiar with Computer languages such as C, C++, perl/TCL/C-shell;

• Be familiar with DC、PT、FM、DFT;

• Self-motivated and good communication skills.